Method of fabricating semiconductor devices

ABSTRACT

The invention is a method of fabricating semiconductor devices which have the uniform avalanche breakdown junctions characteristic of prior art mesa device structures while retaining the desirable passivation and overlay contact features characteristic of planar structures. An important feature is based on the fact that the bulk increases when silicon is converted to the oxide whereby depressions in a silicon body can be filled by selective oxidation of the regions of the depressions.

United States Patent Murphy 1 1 Reissued Dec. 16, I975 METHOD OFFABRICATING $512,054 5/1970 0611111 Ct 111 517/155 AK SENUCONDUCTORDEVICES 3519504 7/1970 Cuomo 11 1, BIT/Z35 3.5311343 9/1970 lrie et a1.3 l 7;148/Z35;l8fi Inventor: Bernard Thomas p y New 5,554234 111/1971)Cluenger 3l7;1-18/Z35;18(1 Providence, NJ. 3.550.256 12/1971) D1331317/235 3.615.929 111/1971 Portn 1y 1 1 1 317/235 UA [731 AssgneeiTelephme 3 4x125 3/1972 P611161 517/255 R Incorporated, Murray Hill, NJFOREIGN PATENTS OR APPLICATIONS [22] Filed: Aug. 10, 1972 6x651411164/1968 Netherlands .1 317/235 Ak [211 App]. No: 279,701 704.674 4/1968Belgium .1 317/235 AK 826.343 10/1969 canatlamuun 317/ AK Related US.Patent Documents Reissue of: OTHER PUBLICATIONS [641 patent No: 3 649386 van Gelder et al., Journal of the Electrochemical Soci- Issued;Nlar. 1 1972 ety, Etching OfSlllCOn Nitride, v61. 113. NO. 12 l Appl.N0. 723,529 3159 1966- Filed: Apr. 23, I968 Primary Examiner-William D.Larkms 152 U.S. c1. 148/175; 148/187' 357/49 8 or Housewwn' 357/50;357/56 Urbano [51] Int. Cl. H0ll 7/36; H011 7/50 [58] Field of Search317/235 E, 235 F, 235 AK; 1 1 ABSTRACT 9 5O 56 The invention is a methodof fabricating semiconductor devices which have the uniform avalanchebreak 1 Refefemes Cled down junctions characteristic of prior art mesadevice UNITED STATES PATENTS structures while retaining the desirablepassivation and 33361465 6/1968 D00 N 3171235 F overlay contact featurescharacteristic of planar struc- 33901)) 6/1968 Manchester y y y w y3|7/335 AY tures. An important feature is based on the fact that3.437533 4/1969 Dingwall 148/187 the bulk increases when silicon isconverted to the 3.442.011 5/1969 Strieter 1 29/578 oxide wherebydepressions in a silicon body can be 1 3 5/1969 Engbe" 7 148/187 filledby selective oxidation of the regions of the dc- 3,461 003 8/196916614566. Jr. 11 148/175 pressions. 3 479237 11/1969 Bergh et a1.3l7;l48/23S;187 1484.313 12 1969 TaLlChl er al. 148/187 5 Claims. 8Drawing Flgures 22 2/ l4 P (/3 23 I? 12 Reissued Dec. 16,1975 Sheet 1012Re. 28,653

22 2/ la P 23 FIG.

I mw

FIG. 2

FIG. 6

Reissued Dec. 16, 1975 Sheet 2 of2 Re. 28,653

METHOD OF FABRICATING SEMICONDUCTOR DEVICES Matter encloud in heavybrackets appears in the original patent but forms no part of thisreissue specification; matter printed in italics indicates the additionsmade by reissue.

BACKGROUND OF THE INVENTION (I) Field of the invention This inventionrelates to the fabrication of semiconductor devices, and moreparticularly relates to a method for filling depressions in asemiconductive body by selectively oxidizing regions of the depression.

The invention has special application to the class of devices having ajunction to be operated in avalanche breakdown. This class includesavalanche photodiodes, PNPN diodes, avalanche transistors, and IMPATTdiodes. IMPATT, an acronym for the I: phase phrase [Mlact Avalanche andTransit Time, is a generic name applied to devices which employ theavalanche and transit time properties of semiconductor structures toproduce negative conductance at microwave and millimeter wavefrequencies. This negative conductance is employed in microwaveamplifiers and oscillators and represents a powerful solid state sourceof high frequency microwave power. It will be convenient to describethis invention specifically in terms of the IM- PATT diode.

(2) Description of the prior art Semiconductor devices fabricatedaccording to the widely used planar process have certain advantagesincluding ease of interconnection of devices by means of overly contactsand including passivation against contamination that would tend todeleteriously afi'ect device characteristics. Highly characteristic ofthe planar process is the diffusion of impurities through a mask to forma PN junction comprising a plane central portion and a curvedsurrounding edge portion which intersects the surface. The geometry ofsuch a junction favors the occurrence of avalanche breakdown at eitherthe surface or at the curved edge of the junction. Unfortunately, suchbreakdown is generally less desirable than breakdown in the bulk overthe larger area central plane portion of the junction.

Various techniques have been suggested to ensure bulk rather thansurface or edge breakdown.

One class of such techniques confines itself substantially to theconventional planar process. Typical of this class is the methoddescribed in US. Pat. 3,345,211, issued Oct. 3, 1967. [n that processthe resistivity of the semiconductor material adjoining the edgeportions of the junction is adjusted to promote bulk breakdown ratherthan surface breakdown. A diode fabricated in that way avoids thesurface breakdown problem, but there still remains the problem that thecurved edge portion of the junction tends to have a lower breakdown thanthe central planar portion. As a consequence, the breakdown tends to belocalized at the relatively small area of the curved edge, thus addingexcess resistance to the diode. This is particularly undesirable for anegative conductance device in that series resistance subtracts directlyfrom the available negative resistance.

Another such technique which has been employed to induce uniformbreakdown of the central planar portion of the junction is the use of aguard ring which is a low resistivity zone surrounding the surface andedge portions of the junction. However, this approach tends to addexcess capacitance and resistance to the diode, both of which limit theavailable output power and high frequency response.

One way to avoid breakdown at the curved edge of a planar junction is toabandon the planar structure and revert to the old mesa structure suchas is depicted in the US. Pat. 3,067,485 to D. F. Ciccolella et al.,issued Dec. ll, 1962. However, mesa structures of the prior art have twodistinct disadvantages. One is the lack of adequate junction passivationwhich causes surface breakdown where the junction comes to the sidewallsof the mesa. A second disadvantage is the obvious difficulty ofinterconnecting elements, such as to form an integrated circuit.

Accordingly, an object of the present invention is a semiconductordevices containing an avalance junction which avoids the tendency toedge or surface breakdown without sacrificing efficiency and high speedof response.

A further object of this invention is a semiconductor structure havingthe desirable avalanche breakdown properties of the older mesastructures while retaining the passivation and overlay contact featuresof planar structures.

A broad object of the invention is a method for selectively fillingdepressions in a semiconductive body.

Another broad object of the invention is a method for forming a mesa ofepitaxially grown semiconductive material over a bulk portion ofsemiconductor material, with the mesa laterally surrounded by a growngenetic oxide of the epitaxial semiconductive material in such a mannerthat the surface of the grown genetic oxide is substantially coplanarwith the surface of the mesa.

SUMMARY OF THE INVENTION To these ends, the present invention provides aprocess for the convenient fabrication of a semiconductor structurewhich includes a mesa-like semiconductor portion within a plane surfaceon which overlay contacts may be formed.

In one aspect an important feature of the method of this invention isthe use of a multirole mask on a semiconductor surface. In one step themask protects a portion of the semiconductor surface while the unmaskedportions are partially etched away. In another step the same maskprevents oxidation of the protected portion of the semiconductor surfacewhile the previously etched portions are oxidized. Subsequently the maskis removed in a solution which does not attack the oxide or thesemiconductor surface.

Another important feature of the method of this invention is that use ismade of the fact that during the thermal oxidation of siliconapproximately 1,000 angstroms of silicon oxide is formed for every 440angstroms of silicon depleted. That is, selective thermal oxidation isemployed to fill depressions in a silicon surface.

As will be apparent from the detailed description set forth hereinbelow,an important first step in accordance with this invention is the formingon the surface of the expitaxial layer of a body which includes asemiconductive epitaxial layer on a semiconductive bulk )ortion a firstmask of a material having the characterstics that it resists etching inan ambient which etches he semiconductor material and that it inhibitsoxidaion of the underlying semiconductor material during a ubsequentstep in which the unmasked portion of the .urface is oxidized and thatit is removable by etching n still another ambient which attacks themask but loes not appreciably attack the grown oxide of the emiconductormaterial. After the mask is formed, the my is immersed in an ambientwhich etches the unnasked portions of the surface of the epitaxial layerbut loes not attack the mask, the etching being allowed to )roceed untilthe unmasked portions of the surface of he epitaxial layer are etched atleast partially through he epitaxial layer to form a mesa. Thereafter,and vithout removing the mask, the body is exposed at an :elevatedtemperature to a second ambient sufficient o oxidize the unmaskedportions of the epitaxial layer ll'ld for a time sufficient that theoxide grown there :xtends essentially completely through the epitaxialayer and planarity thus is substantially restored to the .urface of thebody. Then the mask is removed from he surface to expose the portions ofthe surface previ- )usly underlying the mask; and impurities areintroluced into the now exposed portions of the semiconluctor surface tomodify the conductivity therein, it aeing an important advantage of thisimpurity-introlucing step that the aforementioned grown oxide is lsed asa second mask for enabling selective introducion of impurities into thenow exposed semiconductor 'egions.

In accordance with the preferred embodiment of this nvention, theimpurities introduced into the exposed semiconductor portions are of atype and amount suffi- :ient to form in the mesa a plane rectifyingjunction which intersects the sides of the mesa where such sides 11'6covered by the grown genetic oxide.

In a first described embodiment of this invention an [MPATT diode isprepared essentially as follows. A ightly doped N-type layer is formedon a plane surface )f a more heavily doped N-type monocrystallinesilicon )ody. Typically, the N-type layer is formed by an epiaxialgrowth process. Then the portion of the layer which is to define the I:idode diode junction area is nasked with, for example, silicon nitride,a material iaving the above-described characteristics, and the inmaskedportions of the semiconductor surface are :tched to a predetermineddepth, thus forming a mesa. Jsing the fact that, during thermaloxidation, silicon )xide thickness increases faster than the underlying:ilicon is depleted, the etched regions are then oxidized mtil they aresubstantially filled with oxide, thus restorng a substantially planesurface on which overlay :ontacts may be formed.

Thereafter, the mask is removed from the surface by :tching in asolution which attacks the mask but does tot attack the surroundingsilicon oxide. The final step s a diffusion of impurities into thepreviously masked )ortion of the semiconductor material to form thereintthin P-type zone adjacent the surface, thereby formng a plane PNjunction extending laterally to the sidevalls of the semiconductivemesa. By diffusing to a Iepth such that the jucntion intersects thesidewalls of he mesa at a point beneath the surface of the thermallygrown oxide, passivation of the junction is achieved.

BRIEF DESCRIPTION OF THE DRAWING The invention and its further objectsand features will be more clearly understood from the following detaileddescription taken in conjunction with the drawing in which:

FIG. 1 shows in cross section an IMPA'IT diode fabricated in accordancewith this invention;

FIGS. 2 through 6 show the IMPA'IT diode in various stages of itsmanufacture;

FIG. 7 show a cross section of two diodes connected in series; and

FIG. 8 shows a cross section of a PNPN diode fabricated in accordancewith this invention.

It will be understood that although the following process is describedin terms of a single element, the steps of the process may be performedupon an entire slice which subsequently is divided into several hundredsingle elements.

DETAILED DESCRIPTION In the IMPATT diode l0 depicted in FIG. 1, themonocrystalline silicon body comprises a mesa portion of reduced crosssection on a bulk portion 11 of increased cross section. Bulk portion 11is of low resistivity N-type conductivity while the mesa includes ahigher resistivity N-type zone 15 contiguous with the bulk and a shallowP-type surface zone 14 contiguous with zone 15, thereby forming a planePN junction 13.

The bulk portion surrounding the mesa supports a silicon oxide layer 12of height such that its upper surface is substantially coplanar with theplane surface of the mesa.

Junction 13 intersects the surface of the body at the sidewalls of themesa, and so the region of intersection is buried beneath the surface ofthe silicon oxide, thereby being protected from contamination whichwould deleteriously affect the junction.

Generally, as will appear below, it will be desirable to fonn the mesafrom a layer which is grown expitaxially. This facilitates achieving thedesired high resistivity for layer 15.

A first metal electrode 21 contacts the P-type zone 14 of the diode. Aring contact (not necessarily closed), seen in cross section as metallicregions 22 and 23, contacts the low resistivity N-type substrate 11. Tominimize series resistance, zones 22 and 23 are advantageously as closeas possible to the mesa, subject only to the provision that the contactsdo not in any way interfere with the space charge depletion regionassociated with junction 13.

It will be noted in FIG. 1 than an optional second insulating layer 16has been formed over the surface of both the oxide and the semiconductorportions of the IMPATT diode for the purpose of providing furtherprotection against contamination. Layer 16 may be of silicon nitride,aluminum oxide, or zirconium oxide, or of any other material known toprovide protection against contamination.

The N-type region 15 is advantageously adjusted in thickness andresistivity such that when junction 13 is reverse-biased, that portionof the space charge depletion region which extends into layer 15 shouldapproach interface 17 between layer 15 and substrate 11 when theelectric field in the space charge depletion region is at the thresholdof avalanche breakdown.

If avalanche breakdown occurs before region 15 is swept out, both the DCbias current and any AC signal current is forced to flow through part ofthe relatively high resistivity region 15, thereby adding seriesresistance to the IMPATT diode and thereby detracting from any negativeresistance which is produced.

On the other hand, the space charge region of junction 13 cannot extendsignificantly beyond interface 17 due to the high density of free chargecarriers in substrate 11. It has been found that if avalanche breakdownrequires a voltage significantly higher than that voltage necessary tojust deplete layer of free charge carriers, the high frequencyoscillations can grow in magnitude until the device is thermallydestroyed. Though this problem is not well understood, it is avoided bythe above-suggested relation between the thickness and resistivity oflayer 15.

In accordance with the presently described embodiment of the invention,an IMPATT diode of the kind shown in FIG. 1 is fabricated as follows:

Referring to FIG. 2, the starting material is a monocrystalline siliconwater 1 1 having a very heavy concentration of arsenic impurity suchthat the resistivity is less than about 00015 ohm-centimeter. On onesurface there is grown, in conventional fashion, a one micron thickepitaxial layer 31 in which arsenic again is the predominant impuritybut of lesser concentration such that the resistivity of the epitaxiallayer is about 0.05 ohm-centimeter.

A 2000 angstroms thick masking layer 32, for example, of siliconnitride, is then deposited on epitaxial layer 31 by the conventionalprocess including pyrolitic decomposition of an organic silane.

As will become more evident hereinbelow, masking layer 32 serves amultiple function, and as such will advantageously have the followingcharacteristics It should not be appreciably etched by the ambient(liquid or gaseous) which is to be used subsequently to etch silicon.Further, it should be etched by an ambient which will appreciably etchneither silicon nor silicon oxide. In addition, during subsequentthermal oxidation of the silicon body, layer 32 should prevent oxidationof silicon material covered by that layer. Finally, layer 32 should notform, with the underlying silicon, any alloys, compounds, or mixtureswhich are not conveniently removed without damaging the surroundingsilicon and silicon oxide.

The next processing step is the removal of portions of layer 32 from allregions of the surface of epitaxial layer 31 except those under which arectifying junction will be subsequently formed. This removal isaccomplished, for example, by forming a photoresist film or coatingselectively over portions of the layer 32; etching the exposed portionsof layer 32 in a solution of phosphoric acid maintained at a temperatureof about 180 C; and then dissolving the remaining photoresist in astandard solution intended therefor.

Then by conventional techniques, such as etching in hydrofluoric acid,the now exposed portions of the semiconductor surface are etched for atime sufficient to remove about 70 percent, i.e., about 0.7 micron ofepitaxial layer 31. The resulting mesa-like structure is shown in FIG. 3wherein all but a central portion of the epitaxial layer has been etchedleaving the epitaxial zone 41 covered by the silicon nitride mask 42. Asdepicted, some undercutting typically occurs.

Then, as shown in FIG. 4, thermal oxidation of the entire structure atabout 1050 C. in steam for about two hours converts the unprotectedportions of epitaxial layer 31 to oxide.

Inasmuch as about 1,000 angstroms of silicon oxide is formed for every440 angstroms of underlying silicon depleted, the oxidation step isadvantageously adjusted such that the formed oxide zones 51 and 52substantially fill the voids created by the etching and thus restore asubstantially planar surface 53, as shown in FIG. 4.

The next step is to remove the silicon nitride mask 41 by immersing thebody in a bath of hot (about C C) phosphoric acid which does not attacksilicon or silicon oxide appreciably, This leaves the structure shown inFIG. 5.

It will be noted from FIG. 5 that all but a central portion of epitaxiallayer 31 has been removed, thus leaving a mesa-like structure completelysurrounded laterally by a passivating layer of silicon oxide whichserves the double purpose of restoring a substantially plane surface andof passivating the sidewalls of the mesa.

The next step takes advantage of the known fact that silicon oxide is aneffective mask against the diffusion of boron. The structure shown inFIG. 5 is cleaned in conventional fashion and then placed in a diffusionfurnace such that boron is diffused into the exposed surface of the mesato produce, as shown in FIG. 6, a shallow zone 14 of P-type conductivityhaving a sheet I: resistivilty resistivity of about 500 ohms per square.

It will be noted in FIG. 6 that PN junction 13, formed between diffusedzone 14 and the undiffused remainder of epitaxial zone 15, issubstantially planar, i.e., free of curved portions. In addition,junction 13 has been formed at a depth lower than the surface 53 of theoxide zones 51 and 52 so that all points, such as 61 and 62, at whichthe junction 13 intersects the sidewalls of the mesa are covered andthus passivated by the oxide.

Referring again to FIG. 1, it will be apparent that a variety ofarrangements may be adopted for accomlishing actual electrical contactto the semiconductor zones. A particularly advantageous techniqueincludes the use of a beam lead technology such as disclosed in the M.P. Lepselter Pat. 3,335,338, issued Aug. 8, 1967.

Similarly, it will be apparent to those skilled in the semiconductorintegrated circuit art that two or more such diodes may be formed andinterconnected electrically on a common semiconductor substrate, asshown in FIG. 7.

The two diodes 71 and 72 shown in FIG. 7 each are identical to the diodeof FIG. 1. It will be apparent that the two diodes can be formed on acommon N-type substrate and then electrically isolated by the removal ofsemiconductor material, as shown to form air gap 73 and, thus, to leavean air-isolated structure, such as disclosed in the US. Pat. 3,335,338to MP. Lepselter, issued Aug. 8, I967.

More particularly, FIG. 7 shows the two identical diodes 71 and 72connected electrically in series by the relatively thick metallic beam76 which is attached at the one end to a portion of the ring contact(shown in cross section as zones 74 and 75) to diode 71. The other endof beam 76 is attached to the dot contact to diode 72. Beam 76 is showncrossing over, but not contacting, metallic zone 77 (which is a crosssection of the ring contact to diode 72), and, as such, may beadvantageously formed by the techniques in US. Pat. 3,461,524 issuedAug. 19, 1969 to M. P. Lepselter, and assigned to the same assignee asthis application.

Still further, it will be apparent that the method of this invention maybe employed to fabricate a diode requiring multiple difiusions such as,for example, the PNPN diode shown in FIG. 8.

Referring to FIG. 8, first, there is formed a monocrystalline substrate81 of relatively low resistivity N-type :onductivity having a thin layer82 of relatively high resistivity P-type conductivity thereon. Amultipurpose mask is employed as described hereinbefore in relation tothe first embodiment to enable etching of the surrounding material toform a mesa and then to enable thermal oxidation of the surroundingetched regions to substantially reform a plane surface 83 with the topof the mesa 84. The multipurpose mask is removed and subsequentsuccessive diffusions are employed to form first the N-type zone 85 andthen to convert the surface portion of zone 85 to the shallow P-typezone 86. Electric contacts are made to the front and/or the back of thewafer in accordance with conventional techniques.

in addition, the method of this invention may be employed to fabricatean avalanche photodiode simply by forming a structure, such as isdescribed with refer ence to FIG. 1, with the exception that atransparent or serpentine-type electrode pattern is formed on thesurface of the zone above the junction, and a conventional electrode isformed either on the back of the wafer or on the front, such as zones 22and 23 in FIG. 1. More particular information relating to fabrication ofavalanche photodiodes may be found in US. Pat. 3,514,846 issued June 2,1970 to W. T. Lynch, and assigned to the same assignee as thisapplication.

It will be understood that the specific embodiments described are merelyillustrative of the general principles of the invention and that variousmodifications are feasible without departing from the spirit and scopeof the invention. That is, the method of this invention is of generalapplicability for increasing the planarity of a silicon wafer byselective thermal oxidation.

More particularly, it will be evident that the inven tion may beemployed to form passivated plane junctions free of curved edges inother devices, such as avalanche transistors or integrated circuits.

Still further, it will be apparent that materials other than thosesepcifically specifically mentioned obviously may be used instead. Forexample, aluminum oxide may be used instead of silicon nitride for themultipurpose masking layer.

What is claimed is:

1. A method of fabricating a semiconductor device comprising the stepsof:

forming on the surface of the epitaxial layer of a body which includes asemiconductive epitaxial layer on a semiconductive bulk portion a firstmask of a material having the characteristics that it resists etching ina first ambient which etches the semiconductor material, it inhibitsoxidation of the underlying semiconductor material during a subsequentstep in which the unmasked portion of the surface is oxidized, and it isremovable by etching in a second ambient which attacks the mask but doesnot appreciably attack the grown oxide of the semiconductor material;

immersing the body in the first ambient so that the unmasked portions ofthe surface of the eptiaxial layer are removed by etching at leastpartially through the epitaxial layer to form a mesa;

exposing the body at an elevated temperature to a second ambientsufficient to oxidize the unmasked portions of the epitaxial layer for atime sufficient that the oxide grown there extends essentiallycompletely through the epitaxial layer and planarity is substantiallyrestored to the surface of the body; removing the mask from the surfaceto expose the portions of the surface thereunderlying; and introducingimpurities into the exposed semiconductor portions to modify theconductivity therein, this lastmentioned step using the aforementionedgrown oxide as a second mask for enabling selective introduction ofimpurities into the exposed semiconductor regions] I: 2. A method asrecited in claim 1 wherein the impurities introduced into the exposedsemiconductor portions are of a type and amount sufficient to form inthe mesa a plane rectifying junction which intersects the sides of themesa where such sides are covered by the grown oxide. II

[3. A method as recited in claim 1 wherein the resistivity of theepitaxial layer is different from the resistivity of the bulk portion. 1

I: 4. A method as recited in claim 1 wherein the material for said maskis silicon nitride. I

I: 5. The method recited in claim 1 further characterized in that thesemiconductor material is silicon] [6. The method recited in claim 3further characterized in that the material for said first mask isselected from the group consisting of silicon nitride and aluminumoxide.

I 7. The method recited in claim 5 further characterized in that thesemiconductor body comprises a low resistivity substrate and a higherresistivity epitaxial layer thereon] 8. The method recited in claim 7further characterized in that the introduced impurities convert at leasta portion of the epitaxial layer to a zone of conductivity type oppositeto that of the epitaxial layer] I: 9. The method recited in claim 5wherein the silicon body includes a one micron thick N-type epitaxiallayer on a thicker bulk portion,

the first mask is of a material selected from the group consisting ofsilicon nitride and aluminum oxide, the unmasked regions are etched to adepth of about 0.7 micron, and

the first mask is removed by etching in a solution of phosphoric acidmaintained at about 180 C.

10. The semiconductor device fabricated accordin to claim 9.]

11. The semiconductor device fabricated according to claim 1.

12. A method of fabricating a semiconductor device comprising the stepsof:

first forming a semiconductive epitaxial layer on a semiconductive bulkportion, the bulk portion and the layer constituting a semiconductivebody;

second forming on the surface of the epitaxial layer a first mask of amaterial having the characteristics that it resists etching in a firstambient which etches the semiconductor material, it inhibits oxidationof the underlying semiconductor material during a subsequent step inwhich the unmasked portion of the surface is oxidized, and it isremovable by etching in a second ambient which attacks the mask but doesnot appreciably attack the grown oxide of the semiconductor material;

immersing the body in the first ambient so that the unmasked portions ofthe surface of the epitaxial layer are removed by etching at leastpartially 9 through the epitaxial layer to form a mesa; exposing thebody at an elevated temperature to a second ambient sufficient tooxidize the unmasked portions of the epitaxial layer for a timesufficient that the oxide grown there extends essentially completelythrough the epitaxial layer and planarity is substantially restored tothe surface of the body; removing the mask from the surface to exposethe portions of the surface thereunderlying; introducing impurities into the exposed semiconductor portions to modify the conductivitytherein, this last-mentioned step using the aforementioned grown oxideas a second mask for enabling selective introduction of impurities intothe exposed semiconductor regions; and

characterized in that:

4. the unmasked regions are etched to a depth of about 0.7 micron, and

5. the first mask is removed by etching in a solution of hot phosphoricacid.

13. A method as recited in claim 12 wherein the impurities introducedinto the exposed semiconductor portions are of a type and amountsufficient to form in the mesa a plane rectifying junction whichintersects the sides of the mesa where such sides are covered by thegrown oxide.

14. A method recited in claim 13 further characterized in that thesemiconductor body comprises a low resistivity substrate and a higherresistivity epitaxial layer thereon.

15. A method recited in claim 14 further characterized in that theintroduced impurities convert at least a portion of the epitaxial layerto a zone of conductivity type opposite to that of the epitaxial layer.

16. A method as recited in claim 15 wherein the impurities introducedform in said zone P-type conductivity in the upper part of the mesa, anN-type zone remaining between the P-type zone and the bulk portion, andwherein electrical contacts are made to the P-type zone and the bulkportion so that the device is capable of functioning as an IMPATT diode.

1. the semiconductor material is silicon;
 1. THE SEMICONDUCTOR MATERIALIS SILICON;
 2. THE FIRST FORMING STEP PRODUCES AN EPITAXIAL SILICONLAYER WHICH IS ABOUT ONE MICRON THICK ON A THICKER BULK PORTION ANDWHICH IS DOPED DIFFERENTLY FROM THE BULK PORTION;
 2. the first formingstep produces an epitaxial silicon layer which is about one micron thickon a thicker bulk portion and which is doped differently from the bulkportion;
 3. the first mask is of a material selected from the groupconsisting of silicon nitride and aluminum oxide,
 3. THE FIRST MASK ISOF A MATERIAL SELECTED FROM THE GROUP CONSISTING OF SILICON NITRIDE ANDALUMINUM OXIDE,
 4. THE UNMASKED REGIONS ARE ETCHED TO A DEPTH OF ABOUT0.7 MICRON, AND
 4. the unmasked regions are etched to a depth of about0.7 micron, and
 5. the first mask is removed by etching in a solution ofhot phosphoric acid.
 5. THE FIRST MASK IS REMOVED BY ETCHING IN ASOLUTION OF HOT PHOSPHORIC ACID.
 12. A METHOD FOR FABRICATING ASEMICONDUCTOR DEVICE COMPRISING THE STEPS OF: FIRST FORMING ASEMICONDUCTIVE EPITAXIAL LAYER ON A SEMICONDUCTIVE BULK PORTION, THEBULK PORTION AND THE LAYER CONSTITUTING A SEMICONDUCTIVE BODY; SECONDFORMING ON THE SURFACE OF THE EPITAXIAL LAYER A FIRST MASK OF A MATERIALHAVING THE CHARACTERISTICS THAT IS RESISTS ETCHING IN A FIRST AMBIENTWHICH ETCHES THE SEMICONDUCTOR MATERIAL, IT INHIBITS OXIDATION OF THEUNDERLYING SEMICONDUCTOR MATERIAL DURING A SUBSEQUENT STEP IN WHICH THEUNMASKED PORTION OF THE SURFACE IS OXIDIZED, AND IT IS REMOVABLE BYETCHING IN A SECOND AMBIENT WHICH ATTACKS THE MASK BUT DOES NOTAPPRECIABLY ATTACK THE GROWN OXIDE OF THE SEMICONDUCTOR MATERIAL;IMMERSING THE BODY IN THE FIRST AMBIENT SO THAT THE UNMASKED PORTIONS OFTHE SURFACE OF THE EPITAXIAL LYER ARE REMOVED BY ETCHING AT LEASTPARTIALLY THROUGH THE EPITAXIAL LAYER TO FORM A MESA; EXPOSING THE BODYAT AN ELVATED TEMPERATURE TO A SECOND AMBIENT SUFFICIENT TO OXIDIZE THEUNMASKED PORTIONS OF THE EPITAXIAL LAYER FOR A TIME SUFFICIENT THAT THEOXIDE GROWN THERE EXTENDS ESSENTIALLY COMPLETELY THROUGH THE EPITAXIAL13. A method as recited in claim 12 wherein the impurities introducedinto the exposed semiconductor portions are of a type and amountsufficient to form in the mesa a plane rectifying junction whichintersects the sides of the mesa where such sides are covered by thegrown oxide.
 14. A method recited in claim 13 further characterized inthat the semiconductor body comprises a low resistivity substrate and ahigher resistivity epitaxial layer thereon.
 15. A method recited inclaim 14 further characterized in that the introduced impurities convertat least a portion of the epitaxial layer to a zone of conductivity typeopposite to that of the epitaxial layer.
 16. A method as recited inclaim 15 wherein the impurities introduced form in said zone P-typeconductivity in the upper part of the mesa, an N-type zone remainingbetween the P-type zone and the bulk portion, and wherein electricalcontacts are made to the P-type zone and the bulk portion so that thedevice is capable of functioning as an IMPATT diode.